Verifying parametrised hardware designs via counter automata

Authors:
A. Smrčka;T. Vojnar
Affiliations:
FIT, Brno University of Technology, Brno, Czech Republic;FIT, Brno University of Technology, Brno, Czech Republic
Venue:
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
Year:
2007

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Abstract

The paper presents a new approach to formal verification of generic (i.e. parametrised) hardware designs specified in VHDL. The proposed approach is based on a translation of such designs to counter automata and on exploiting the recent advances achieved in the area of their automated formal verification. We have implemented the proposed translation. Using one of the state-of-the-art tools for verification of counter automata, we were then able to verify several non-trivial properties of parametrised VHDL components, including a real-life one.