Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Novel Efficient Check Node Update Implementations for Row Weight Matched Min-Sum Algorithm
IMSCCS '07 Proceedings of the Second International Multi-Symposiums on Computer and Computational Sciences
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Factor graphs and the sum-product algorithm
IEEE Transactions on Information Theory
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Recently, wireless local area network (WLAN) requires high-speed and high-reliability for multimedia access at home, office and etc. The WLAN standard: IEEE802.11n, which enhanced them compared with the existing IEEE802.11a/b/g, can achieve a maximum throughput of at least 100Mbps at the medium access control (MAC) layer. In the other hand low density parity check (LDPC) which is among the most powerful error correcting codes (ECC), can achieve performance close to the Shannon limit. In this paper we report RTL design of a high-throughput LDPC decoder using the min-sum algorithm.