A novel four-step search algorithm for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
| Hi-index | 0.00 |
This paper proposes an H.264/AVC motion estimation algorithm and its architecture. The proposed algorithm is performed in 2 stages and uses ±18 search range. In the proposed algorithm, search points form square patterns, and the patterns are center-biased. Stage 1 compares 152 search points with each other. In this stage, the interval between the outer search points is wider than that of the inner search points. Stage 2 uses ±2 full search around the point selected in the stage 1. This paper also proposes an integer motion estimation unit to support the proposed algorithm. The architecture is composed of current block buffer, processing element, hadamard transform, adder tree, accumulator, comparator, motion vector generator and mode decision unit. In the proposed architecture, one reference block can be processed for 16 cycles and next reference block can be processed without delay. The architecture efforts to minimize hardware cost for mobile devices. The reference block buffer only uses small size block to store 20×20 pixels because it reuses most of reference block data. The mode decision unit uses proposed mode decision algorithm with non Rate Distortion Optimization (RDO) to enhance the accuracy of the estimation and supports 3 multi-reference frames, 7 variable block sizes and early termination mode. It takes 3000-9000 cycles to process one macroblock and it is enough to achieve 30 frames per second in CIF sequences at 150 MHz.