RFID Handbook: Fundamentals and Applications in Contactless Smart Cards and Identification
RFID Handbook: Fundamentals and Applications in Contactless Smart Cards and Identification
CMOS Circuit Design, Layout, and Simulation, Second Edition
CMOS Circuit Design, Layout, and Simulation, Second Edition
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This paper proposes a design of a power harvester for a semi-passive RFID Tag. A tunable impedance transformation circuit is inserted between the antenna and the rectifier unit to maximize the power delivered to the rectifier of a tag and minimize reflections from the antenna input port. A power harvester for the UHF band of 950 MHz has been designed based on a 0.35 µm CMOS technology. This impedance matching is designed to maximize efficiency by characterizing both the tunable impedance transformation circuit and the conventional rectifier circuit. The antenna is modeled as an RF source with series impedance ZS of 50Ω while the rectifier is modeled an impedance ZL, which is approximated from the process and design parameters of the NMOS transistors used in the conventional NMOS rectifier. These two impedances are used to find optimal matching parameters of the chosen lowpass LL matching circuit. The simulation results show that the required voltage for a 1.2V secondary battery can be achieved with the tunable impedance matching circuit and conventional 2-stage rectifier. The DC output of the rectifier yields the maximum DC voltage of 1.77V, the maximum average current of 4.72µA, and the power conversion efficiency of 15.85% for the input RF power of -14.47dBm at the battery voltage of 1.2V.