Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
An algebraic approach to network coding
IEEE/ACM Transactions on Networking (TON)
Deterministic network coding by matrix completion
SODA '05 Proceedings of the sixteenth annual ACM-SIAM symposium on Discrete algorithms
The encoding complexity of network coding
IEEE/ACM Transactions on Networking (TON) - Special issue on networking and information theory
XORs in the air: practical wireless network coding
Proceedings of the 2006 conference on Applications, technologies, architectures, and protocols for computer communications
Network coding for routability improvement in VLSI
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Flattened butterfly: a cost-efficient topology for high-radix networks
Proceedings of the 34th annual international symposium on Computer architecture
Improving FPGA routability using network coding
Proceedings of the 18th ACM Great Lakes symposium on VLSI
IEEE Transactions on Information Theory
IEEE Transactions on Information Theory
Polynomial time algorithms for multicast network code construction
IEEE Transactions on Information Theory
On average throughput and alphabet size in network coding
IEEE Transactions on Information Theory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
In this paper, we describe a low-area, reduced-power on-chip point-to-point bidirectional communication scheme for heavily pipelined systems. When data needs to be transmitted bidirectionally between two on-chip locations, the traditional approach resorts to either using two unidirectional wires, or to using a single wire (with a unidirectional transfer at any given time instant). In contrast, our bidirectional communication scheme allows data to be transmitted simultaneously between two on-chip locations, with a single wire performing the bidirectional data transfer. Our approach borrows ideas from the emerging area of network coding (in the field of communication). By utilizing coding units (which also serve the purpose of buffering the signals) along the wire between the two endpoints, we are able to achieve the same throughput as a traditional approach, while reducing the total area utilization by about 49.8% (thereby reducing routing congestion), and the total power consumption by about 11.5%. The area and power results include the contribution of routing wires, coding units, drivers, the clock distribution network and the required reset wire. Our bidirectional communication approach is ideally suited for heavily pipelined data intensive systems.