The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
The RAISE specification language
The RAISE specification language
System Design with SystemC
Formal Development and Verification of a Distributed Railway Control System
IEEE Transactions on Software Engineering
Unified Modeling Language Reference Manual, The (2nd Edition)
Unified Modeling Language Reference Manual, The (2nd Edition)
Software Engineering 1: Abstraction and Modelling (Texts in Theoretical Computer Science. An EATCS Series)
Software Engineering 2: Specification of Systems and Languages (Texts in Theoretical Computer Science. An EATCS Series)
Software Engineering 3: Domains, Requirements, and Software Design (Texts in Theoretical Computer Science. An EATCS Series)
Test automation for hybrid systems
Proceedings of the 3rd international workshop on Software quality assurance
A Domain-Specific Framework for Automated Construction and Verification of Railway Control Systems
SAFECOMP '09 Proceedings of the 28th International Conference on Computer Safety, Reliability, and Security
Automatic verification of parametric specifications with complex topologies
IFM'10 Proceedings of the 8th international conference on Integrated formal methods
Using domain specific languages to support verification in the railway domain
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
The Journal of Supercomputing
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This paper describes a complete model-based development and verification approach for railway control systems. For each control system to be generated, the user makes a description of the applicationspecific parameters in a domain-specific language. This description is automatically transformed into an executable control system model expressed in SystemC. This model is then compiled into object code. Verification is performed using four main methods applied to different levels: (0) The domain-specific description is validated wrt. internal consistency by static analysis. (1) The crucial safety properties are verified for the SystemC model by means of bounded model checking. (2) The object code is verified to be I/O behavioural equivalent to the SystemC model from which it was compiled. (3) The correctness of the hardware/software integration is checked by automated testing.