New architecture of wavelet packet transform using parallel filters

Authors:
Hossein Amiri Farahani;Majid Mashayekhi Nezamabadi
Affiliations:
Department of Electrical Engineering Faculty, Pakdasht Sama College of Azad University, Tehran, Iran;Department of Electrical Engineering Faculty, Pakdasht Sama College of Azad University, Tehran, Iran
Venue:
ISPRA'10 Proceedings of the 9th WSEAS international conference on Signal processing, robotics and automation
Year:
2010

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Abstract

In this paper, based on the word-serial pipeline architecture and parallel filter processing, a new architecture for direct and inverse wavelet packet transforms is introduced. This architecture increase the speed of the wavelet packet transforms. In this design a word-serial architecture able to compute a complete wavelet packet transform (WPT) binary tree in an on-line fashion, but easily configurable in order to compute any required WPT sub tree, is proposed. In this architecture, a high-pass filter and a low-pass filter are used concurrently, in order to compute the new coefficients. This architecture is suitable for the high-speed on-line applications. With this architecture, the speed of the wavelet packet transforms is increased with a factor two, but the occupied area of the circuit is less than double. This architecture can be applied to any levels tree structure with any filter coefficients length.