The case for a single-chip multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Computer
Dynamic Partitioning of Shared Cache Memory
The Journal of Supercomputing
Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
Best of Both Latency and Throughput
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Conjoined-Core Chip Multiprocessing
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Mitigating Amdahl's Law through EPI Throttling
Proceedings of the 32nd annual international symposium on Computer Architecture
A NUCA substrate for flexible CMP cache sharing
Proceedings of the 19th annual international conference on Supercomputing
The Future Evolution of High-Performance Microprocessors
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Heterogeneous Chip Multiprocessors
Computer
Exploring the cache design space for large scale CMPs
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Power-performance considerations of parallel computing on chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors
IEEE Computer Architecture Letters
Core architecture optimization for heterogeneous chip multiprocessors
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Holistic design for multi-core architectures
Holistic design for multi-core architectures
A unified approach to topology generation and optimal sizing of floorplans
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Homogeneous multi-core architectures come in a variety of floorplans. A large portion of the chip area is occupied by the second level cache memories and the interconnect. Usually, the floorplan is dictated by the interconnect type and the second level cache memory size and by whether large resources on the chip are shared or private. We consider floorplans for a 16-core architecture consisting of identical cores and estimate their areas based on two different processor cores. Then, we focus on an area-efficient and performance-scaling four-partition crossbar-interconnected architecture with third level cache memory and conduct performance modelling and evaluation of the multi-core architecture's memory system. With a database workload and a first level cache miss rate under 20%, the Average Memory Access Time (AMAT) is estimated to be under 20 processor cycles. With higher memory contention resulting into longer bridge queue wait times, the various cache miss rates rate make a more pronounced effect on the Chip Multiprocessors AMAT, necessitating design measures like proper cache sizing. When the size of shared resources becomes too large, recent work in sharing and partitioning large resources in CMP architectures becomes crucial.