Matrix analysis
FPGA implementation of Reed-Solomon codes
Proceedings of the International Conference & Workshop on Emerging Trends in Technology
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An efficient encoder circuit for a systematic Reed-Solomon code with arbitrary parity positions is presented. In contrast to the Reed-Solomon encoder circuits widely available today, the parity symbols produced by this encoder are not restricted to form a block of consecutive parity symbols at the beginning or end of the codeword, but may be spread arbitrarily within the codeword. A general structure of the parity-check matrix for such a code is derived by exploiting the special structure of Vandermonde matrices. From this general parity-check matrix, an expression for the calculation of the Reed-Solomon parity symbols at arbitrary positions within the codeword is found and an efficient hardware implementation of the proposed encoder is designed.