Introduction to Stochastic Search and Optimization
Introduction to Stochastic Search and Optimization
A scalable LDPC decoder ASIC architecture with bit-serial message exchange
Integration, the VLSI Journal
Tracking Forecast Memories in stochastic decoders
ICASSP '09 Proceedings of the 2009 IEEE International Conference on Acoustics, Speech and Signal Processing
Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices
IEEE Transactions on Communications
Fully Parallel Stochastic LDPC Decoders
IEEE Transactions on Signal Processing
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Factor graphs and the sum-product algorithm
IEEE Transactions on Information Theory
Majority-based tracking forecast memories for stochastic LDPC decoding
IEEE Transactions on Signal Processing
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This paper presents a Relaxed Half-Stochastic (RHS) low-density parity-check (LDPC) decoding algorithm that uses some elements of the sum-product algorithm (SPA) in its variable nodes, but maintains the low-complexity interleaver and check node structures characteristic of stochastic decoders. The algorithm relies on the principle of successive relaxation to convert binary stochastic streams to a log-likelihood ratio (LLR) representation. Simulations of a (2048, 1723) RS-LDPC code show that the RHS algorithm can outperform 100-iterations floating-point SPA decoding. We describe approaches for low-complexity implementation of the RHS algorithm. Furthermore, we show how the stochastic nature of the belief representation can be exploited to lower the error floor.