Design and analysis of synchronizable error-resilient arithmetic codes

  • Authors:

  • Hiroyoshi Morita;Ying Zou;Adriaan J. van Wijngaarden

  • Affiliations:

  • Graduate School of Information Systems, University of Electro-Communications, Chofu, Tokyo, Japan;Hitachi Software Engineering Co., Ltd, Shinagawa, Tokyo, Japan;Math. of Networks & Commun. Research Dept., Bell Laboratories, Alcatel-Lucent, Murray Hill, NJ

  • Venue:
  • GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
  • Year:
  • 2009

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Abstract

An error-resilient variable-length arithmetic code is presented whose codewords are represented by binary digits. The input sequence is partitioned in subsequences, each of which is individually encoded using an arithmetic coding scheme with an integrated bit-stuffing technique that restricts the number of consecutive ones in the output sequence. An all-ones sequence of fixed length is appended to serve as a sync marker when the codewords are concatenated. The bit-stuffing technique ensures that the sync markers do not occur anywhere except at the boundaries between the codewords. Expressions for the optimal choice of the marker length and the block length are derived. The performance of the proposed code is determined in terms of redundancy and error resilience. An upper bound on the average error rate is derived and its tightness is confirmed with computer simulations. The proposed code shows to significantly suppress the error rate at the expense of a minimum increase in redundancy.