A Model of Saliency-Based Visual Attention for Rapid Scene Analysis
IEEE Transactions on Pattern Analysis and Machine Intelligence
Algorithms for Defining Visual Regions-of-Interest: Comparison with Eye Fixations
IEEE Transactions on Pattern Analysis and Machine Intelligence
Distinctive Image Features from Scale-Invariant Keypoints
International Journal of Computer Vision
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Computers and Electronics in Agriculture
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In this paper, an attention controlled multi-core architecture is proposed for energy efficient object recognition. The proposed architecture employs two IP layers having different roles for energy efficient recognition processing: the attention/control IPs compute regions-of-interest (ROIs) of the entire image and control the multiple processing cores to perform local object recognition processing on selected area. To this end, a task manager is proposed to perform dynamic scheduling of various ROI tasks from the attention IP to multiple cores in a unit of small-sized grid-tile. Thanks to a number of grid-tile threads generated by the task manager, the utilization of the multiple cores amounts to 92% on average. As a result, the proposed architecture achieves 2.1x energy reduction in multi-core recognition system by indicating processing cores to focus on critical area of the image with a 0.87mJ attention processing. Finally, the proposed architecture is implemented in 0.13@mm CMOS technology and the fabricated chip verifies 3.2x lower energy dissipation per frame than the state-of-the-art object recognition processor.