Toward development of high secure sensor network nodes using an FPGA-based architecture

Authors:
Björn Stelte
Affiliations:
Universität der Bundeswehr München, Neubiberg, Germany
Venue:
Proceedings of the 6th International Wireless Communications and Mobile Computing Conference
Year:
2010

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Abstract

In the last years research on wireless sensor networks (WSN) has focused on how to build power-aware sensor networks. Due to the limited resources an effective, efficient cryptosystem is needed to provide security and at the same time save power and memory. Efficient usage of strong cryptographic algorithms for WSNs is an open problem. To solve this problem we propose in this paper a new architectural concept for WSN sensor nodes. In our concept, power-saving and cost-saving FPGA chips build the main component of our senor nodes. The proposed architecture is of significant importance since it presents a new trend towards providing security for WSNs and reducing power consumption.