Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the value locality of store instructions
Proceedings of the 27th annual international symposium on Computer architecture
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Hacking the Xbox: An Introduction to Reverse Engineering
Hacking the Xbox: An Introduction to Reverse Engineering
Hardware assisted control flow obfuscation for embedded processors
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Pin: building customized program analysis tools with dynamic instrumentation
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Authentication Control Point and Its Implications For Secure Processor Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
New cache designs for thwarting software cache-based side channel attacks
Proceedings of the 34th annual international symposium on Computer architecture
Architecting phase change memory as a scalable dram alternative
Proceedings of the 36th annual international symposium on Computer architecture
A durable and energy efficient main memory using phase change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Scalable high performance main memory system using phase-change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Hybrid cache architecture with disparate memory technologies
Proceedings of the 36th annual international symposium on Computer architecture
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A Phase Change Memory as a Secure Main Memory
IEEE Computer Architecture Letters
SAFER: Stuck-At-Fault Error Recovery for Memories
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
A frequent-value based PRAM memory architecture
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Emerging non-volatile memories: opportunities and challenges
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SCMFS: a file system for storage class memory
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
Preventing PCM banks from seizing too much power
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Pay-As-You-Go: low-overhead hard-error correction for phase change memories
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Point and discard: a hard-error-tolerant architecture for non-volatile last level caches
Proceedings of the 49th Annual Design Automation Conference
Age-based PCM wear leveling with nearly zero search cost
Proceedings of the 49th Annual Design Automation Conference
Write performance improvement by hiding R drift latency in phase-change RAM
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 39th Annual International Symposium on Computer Architecture
PreSET: improving performance of phase change memories by exploiting asymmetry in write times
Proceedings of the 39th Annual International Symposium on Computer Architecture
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the ACM SIGMETRICS/international conference on Measurement and modeling of computer systems
Phase-change memory: An architectural perspective
ACM Computing Surveys (CSUR)
Bit mapping for balanced PCM cell programming
Proceedings of the 40th Annual International Symposium on Computer Architecture
Zombie memory: extending memory lifetime by reviving dead blocks
Proceedings of the 40th Annual International Symposium on Computer Architecture
Optimizing video application design for phase-change RAM-based main memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A case study on the application of real phase-change RAM to main memory subsystem
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Bloom filter-based dynamic wear leveling for phase-change RAM
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
SCMFS: A File System for Storage Class Memory and its Extensions
ACM Transactions on Storage (TOS)
Dynamic interval polling and pipelined post I/O processing for low-latency storage class memory
HotStorage'13 Proceedings of the 5th USENIX conference on Hot Topics in Storage and File Systems
Aegis: partitioning data block for efficient recovery of stuck-at-faults in phase change memory
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies
ACM Transactions on Architecture and Code Optimization (TACO)
NVM duet: unified working memory and persistent store architecture
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
ARI: Adaptive LLC-memory traffic management
ACM Transactions on Architecture and Code Optimization (TACO)
An efficient run-time encryption scheme for non-volatile main memory
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Endurance-aware cache line management for non-volatile caches
ACM Transactions on Architecture and Code Optimization (TACO)
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Phase change memory (PCM) is an emerging memory technology for future computing systems. Compared to other non-volatile memory alternatives, PCM is more matured to production, and has a faster read latency and potentially higher storage density. The main roadblock precluding PCM from being used, in particular, in the main memory hierarchy, is its limited write endurance. To address this issue, recent studies proposed to either reduce PCM's write frequency or use wear-leveling to evenly distribute writes. Although these techniques can extend the lifetime of PCM, most of them will not prevent deliberately designed malicious codes from wearing it out quickly. Furthermore, all the prior techniques did not consider the circumstances of a compromised OS and its security implication to the overall PCM design. A compromised OS will allow adversaries to manipulate processes and exploit side channels to accelerate wear-out. In this paper, we argue that a PCM design not only has to consider normal wear-out under normal application behavior, most importantly, it must take the worst-case scenario into account with the presence of malicious exploits and a compromised OS to address the durability and security issues simultaneously. In this paper, we propose a novel, low-cost hardware mechanism called Security Refresh to avoid information leak by constantly migrating their physical locations inside the PCM, obfuscating the actual data placement from users and system software. It uses a dynamic randomized address mapping scheme that swaps data using random keys upon each refresh due. The hardware overhead is tiny without using any table. The best lifetime we can achieve under the worst-case malicious attack is more than six years. Also, our scheme incurs around 1% performance degradation for normal program operations.