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Computer Networks and ISDN Systems
A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Power Aware Management of Packet Switches
HOTI '07 Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects
Dynamic Programming and Optimal Control, Vol. II
Dynamic Programming and Optimal Control, Vol. II
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In this paper we propose two advanced algorithms which allow for both differentiated quality-of-service (QOS) and power conservation in input-queued packet switches. These algorithms are based on two core ideas: first, we assume that the switch can operate in a number of operational speed modes; a higher speed mode serves more packets per time slot at the cost of higher power consumption. Second, each virtual output queue may tolerate a certain low backlog which is called a target in this setting. Thus, one can control power by adjusting the speed mode and QOS by setting the targets appropriately. We first survey previous work to provide the necessary background behind our approach. We then describe our algorithms and evaluate their performance experimentally through simulation. Our preliminary results show that these new procedures offer significant performance gains compared to existing approaches.