FPGA implementation of trellis shaping to control peak power for PSK signals

  • Authors:

  • Hiroyuki Kitagawa;Makoto Tanahashi;Hideki Ochiai

  • Affiliations:

  • Graduate School of Engineering, Yokohama National University, Yokohama, Kanagawa, Japan;Graduate School of Engineering, Yokohama National University, Yokohama, Kanagawa, Japan;Graduate School of Engineering, Yokohama National University, Yokohama, Kanagawa, Japan

  • Venue:
  • ICC'09 Proceedings of the 2009 IEEE international conference on Communications
  • Year:
  • 2009

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Abstract

Single-carrier (SC) transmission is considered as a promising candidate for the uplink of the next generation cellular systems due to its relatively low peak-to-average power ratio (PAR) compared to multi-carrier systems such as orthogonal frequency division multiplexing (OFDM). In SC systems, bandwidth efficiency can be effectively enhanced by the use of waveform shaping filter with low roll-off factor. However, as a price, nonnegligible increase of PAR is incurred in pulse-shaped signals even for phase shift keying (PSK) modulation. To balance both low PAR and high bandwidth efficiency, the authors have recently proposed a novel PAR reduction technique for SC-PSK based on trellis shaping (TS). In this paper, we evaluate its effectiveness and feasibility through implementation with field programmable gate array (FPGA) and testbed experiments with a sample RF power amplifier (PA).