Data Structures and Algorithms
Data Structures and Algorithms
A Parallel and Pipelined Execution of H.264/AVC Intra Prediction
CIT '06 Proceedings of the Sixth IEEE International Conference on Computer and Information Technology
Highly parallel rate-distortion optimized intra-mode decision on multicore graphics processors
IEEE Transactions on Circuits and Systems for Video Technology
Intra frame encoding using programmable graphics hardware
PCM'07 Proceedings of the multimedia 8th Pacific Rim conference on Advances in multimedia information processing
Accelerate video decoding with generic GPU
IEEE Transactions on Circuits and Systems for Video Technology
Highly parallel rate-distortion optimized intra-mode decision on multicore graphics processors
IEEE Transactions on Circuits and Systems for Video Technology
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Rate-distortion (RD) optimized intra-prediction mode selection can lead to significant improvement in coding efficiency in intraframe encoding. However, it would incur considerable increase in encoding complexity. In this paper, we investigate how multicore Graphics Processing Units (GPUs) can be efficiently utilized to undertake the task of RD optimized intra mode selection in AVS and H.264 video encoding. Achieving efficient GPU-based intra mode decision, however, could be non-trivial. It is because the mode decision of the current block would depend on the reconstructed data of the neighboring blocks. Therefore, the coding modes of neighboring blocks would need to be computed first before that of the current block can be determined. This dependency poses challenge to computation on multi-core GPUs, which rely heavily on parallel data processing to achieve superior speedups. To address this issue, we analyze the data dependency in intra mode decision, and propose novel greedy-based encoding orders to achieve highly parallel processing. We also prove that the proposed greedy-based orders are optimal in terms of execution time. Experimental results suggest that the proposed GPU-based intra mode decision compares favorably to the counterpart implemented on a single-core CPU.