A feasible VLSI engine for soft-input-soft-output for joint source channel codes

Authors:
Simone Zezza;Guido Masera;Saeid Nooshabadi
Affiliations:
Politecnico di Torino, VLSI Laboratory, Torino, Italy;Politecnico di Torino, VLSI Laboratory, Torino, Italy;Gwangju Inst. of Sci. and Tech., Dept. of Info. and Comm., Gwangju, Republic of Korea
Venue:
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
Year:
2009

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Abstract

This paper proposes for the first time, the very large scale integration (VLSI) architectural techniques for error resilient joint source channel coding (JSCC) of arithmetic codes (AC). When implemented on a 0.13 µm standard cells technology running at 340 MHz, achieves a decoding throughput of up to 125 kbit/s, 58 times better than the standard implementation.