Low power input/output port design using clock gating technique

Authors:
Hyeon-Mi Yang;Sea-Ho Kim;Keun-Sik Park;Hi-Seok Kim
Affiliations:
The Department of Electronics Engineering, Cheongju University, Republic of Korea;The Department of Electronics Engineering, Cheongju University, Republic of Korea;The Department of Electronics Engineering, Cheongju University, Republic of Korea;The Department of Electronics Engineering, Cheongju University, Republic of Korea
Venue:
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Year:
2010

Citing 1
Cited 0

DCG: deterministic clock-gating for low-power microprocessor design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Clock gating is a well-known technique to reduce chip dynamic power. This paper propose a modified clock gating techniques based on ACG(Adaptive Clock Gating) and instruction level clock gating. The proposed clock gating technique reduces not only switching activity of functional blocks in IDLE state but also dynamic power in running state. Our modified ACG can automatically enable or disable the clock of the functional block. The experimental results on some I/O port core in SoC show an average of 19.45% dynamic power reduction comparing to previous ACG technique.