Programmable architecture for flexi-mode QC-LDPC decoder supporting wireless LAN/MAN applications and beyond

Authors:
Dan Bao;Bo Xiang;Rui Shen;An Pan;Yun Chen;Xiao Yang Zeng
Affiliations:
State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;State Key Laboratory of ASIC and System, Fudan University, Shanghai, China
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2010

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Abstract

A programmable architecture is proposed for a flexi-mode quasi-cyclic low-density parity-check code decoder. The proposed architecture has the following advantages: 1) Code rate, length, and pattern can be programmed on the fly; 2) decoding complexity is reduced by algorithm modification; 3) memory read/write operation is reduced by access optimization and hierarchical memory structure; and 4) an early stopping scheme is adopted to give power efficiency, particularly in the low-signal-to-noise-ratio region. A decoder chip is implemented in an SMIC 180-nm 1.8-V CMOS technology. Experimental results show the advantages in terms of flexibility, area, power, and error-correction performance.