Design of a robust multi-channel timing recovery system with imperfect channel state information for 10GBASE-T

  • Authors:

  • Ying-Ren Chien;Wei-Lung Mao;Hen-Wai Tsao

  • Affiliations:

  • Integrated System Laboratory, Graduate Institute of Communication Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan;Department of Electronic Engineering, National Formosa University, Yunlin, Taiwan;Integrated System Laboratory, Graduate Institute of Communication Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan

  • Venue:
  • IEEE Transactions on Circuits and Systems Part I: Regular Papers
  • Year:
  • 2010

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Abstract

The interdependence among multiple channels and the interaction between timing and equalization loops bring new challenges to the design of a multi-channel symbol timing recovery (STR) system for 10GBASE-T. In addition, the nonlinear Tomlinson-Harashima precoding (THP) technique used in the 10GBASE-T system is vulnerable to the imperfect channel state information (CSI). In this paper, we address the problem of timing inaccuracy caused by imperfect CSI and the problem of extracting correct timing information in the presence of channel-interdependence and loop-interaction for 10GBASE-T. This paper proposes a novel averaged-sampling-phase (ASP) hybrid STR scheme, which aligns the sampling clock phase of a single phase-locked loop (PLL) with an average value of the timing information provided by each wire pair so that the impact of the noisy timing information resulting from the imperfect CSI and the timing jitter of the single PLL is reduced. Moreover, a three-phase timing recovery strategy based on our architecture is also designed to correctly extract the timing information and effectively mitigate the loop-interaction. Simulation results demonstrate that the proposed multi-channel STR provides a complete loop-timed solution for 10GBASE-T and achieves a superior performance over conventional approaches in terms of robustness and timing jitter.