How to Sort N Items Using a Sorting Network of Fixed I/O Size
IEEE Transactions on Parallel and Distributed Systems
An Optimal Hardware-Algorithm for Sorting Using a Fixed-Size Parallel Sorting Device
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Radio Network Planning and Optimisation for Umts
Radio Network Planning and Optimisation for Umts
Proceedings of the conference on Design, automation and test in Europe
A comparison of pilot-aided channel estimation methods for OFDMsystems
IEEE Transactions on Signal Processing
IEEE Transactions on Wireless Communications
A Refined Channel Estimation Method for STBC/OFDM Systems in High-Mobility Wireless Channels
IEEE Transactions on Wireless Communications - Part 1
A simple transmit diversity technique for wireless communications
IEEE Journal on Selected Areas in Communications
STBC-OFDM downlink baseband receiver for mobile WMAN
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, a robust channel estimator for high-mobility space-time block code-orthogonal frequency division multiplexing (STBC-OFDM) systems is proposed and applied in IEEE 802.16e systems. A high-performance two-stage channel estimation method is adopted. The proposed architecture reduces computational complexity effectively and improves 85.2% of the hardware implementation. The performances of the proposed design have been demonstrated through the simulation of an STBC-OFDM system with two transmit antennas and one receive antenna. At the vehicle speed of 120 and 240 km/hr for quadrature phase shift keying (QPSK) modulation, the proposed design can achieve the bit-error rate (BER) of about 10-4 and 10-3 without using channel coding. Moreover, it has significant performance improvement as compared with interpolation-based channel estimation methods. The proposed channel estimator implemented in 90 nm CMOS technology can support up to 29.03 Mbps (uncoded) downlink data transmission. The design only requires 859.6 K gates and dissipates 43.71 mW at 83.3 MHz operating frequency with 1 V power supply.