Dual-source-line-bias scheme to improve the read margin and sensing accuracy of STTRAM in sub-90-nm nodes

Authors:
Subho Chatterjee;Sayeef Salahuddin;Saibal Mukhopadhyay
Affiliations:
Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA;Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2010

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Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement

Proceedings of the 45th annual Design Automation Conference

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Abstract

This brief analyzes the circuit-induced challenges to reliability and write current scaling of spin-torque-transfer random access memory (STTRAM). We show that, at sub-90-nm nodes, increased transistor leakage increases the probability of incorrect sensing requiring a higher read current. However, a higher read current can increase the read disturb failure, particularly with a reduced write current. To satisfy the conflicting requirements of read margin and sensing accuracy, we propose a source-line biasing technique. Simulations in predictive 65-nm nodes show that the proposed solution simultaneously reduce the sensing errors and improve the read margin.