Multichannel clock and data recovery: a synchronous approach

Authors:
Ahmed Nassar;Ahmed Emira;Ahmed Nader Mohieldin;Ahmed Hussien
Affiliations:
Department of Electronics and Communications, Faculty of Engineering, Cairo University, Giza, Egypt;Department of Electronics and Communications, Faculty of Engineering, Cairo University, Giza, Egypt;Department of Electronics and Communications, Faculty of Engineering, Cairo University, Giza, Egypt;Department of Electronics and Communications, Faculty of Engineering, Cairo University, Giza, Egypt
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2010

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Abstract

This brief proposes a scalable multichannel clock and data recovery architecture that exploits the synchrony of multiple point-to-point serial links and uses a single voltage-controlled oscillator (VCO) to drive multiple phase detection loops. The proposed architecture can be naturally reduced by design to an ensemble of weakly interacting delay-locked loops. As a result, the jitter peaking problem is asymptotically eliminated, which makes this architecture well suited for use in long-haul repeater chains. Moreover, it allows controlling VCO jitter transfer to the recovered clock without affecting data jitter transfer. The architecture is demonstrated both by a Verilog-A behavioral model along with a rigorous system and statistical analysis.