Construction of non-binary quasi-cyclic LDPC codes by arrays and array dispersions
IEEE Transactions on Communications
Decoder design for RS-based LDPC codes
IEEE Transactions on Circuits and Systems II: Express Briefs
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application of Nonbinary LDPC Cycle Codes to MIMO Channels
IEEE Transactions on Wireless Communications
Design of capacity-approaching irregular low-density parity-check codes
IEEE Transactions on Information Theory
Design and analysis of nonbinary LDPC codes for arbitrary discrete-memoryless channels
IEEE Transactions on Information Theory
Integration, the VLSI Journal
Low-complexity reliability-based message-passing decoder architectures for non-binary LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper addresses decoder design for nonbinary quasicyclic low-density parity-check (QC-LDPC) codes. First, a novel decoding algorithm is proposed to eliminate the multiplications over Galois field for check node processing. Then, a partially parallel architecture for check node processing units and an optimized architecture for variable node processing units are developed based on the new decoding algorithm. Thereafter, an efficient decoder structure dedicated to a promising class of high-performance nonbinary QC-LDPC codes is presented for the first time. Moreover, an ASIC implementation for a (620, 310) nonbinary QC-LDPC code decoder over GF(32) is designed to demonstrate the efficiency of the presented techniques.