Mapping loop nests to multipipelined architecture

  • Authors:

  • R. B. Steinberg

  • Affiliations:

  • Southern Federal University, Rostov-on-Don, Russia 344006

  • Venue:
  • Programming and Computing Software
  • Year:
  • 2010

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Abstract

Mapping of non-perfectly nested loops onto a multipipelined architecture is considered. Formulas for the delays between the pipeline starting times are obtained. Graph models of programs (data dependence graph, lattice graph, and computation graph) are used.