Architecture Design of Fine Grain Quality Scalable Encoder with CABAC for H.264/AVC Scalable Extension

  • Authors:
  • Tzu-Der Chuang;Yu-Jen Chen;Yi-Hau Chen;Shao-Yi Chien;Liang-Gee Chen

  • Affiliations:
  • Department of Electrical Engineering II, National Taiwan University 1, Taipei, Taiwan 10617;Department of Electrical Engineering II, National Taiwan University 1, Taipei, Taiwan 10617;Department of Electrical Engineering II, National Taiwan University 1, Taipei, Taiwan 10617;Department of Electrical Engineering II, National Taiwan University 1, Taipei, Taiwan 10617;Department of Electrical Engineering II, National Taiwan University 1, Taipei, Taiwan 10617

  • Venue:
  • Journal of Signal Processing Systems
  • Year:
  • 2010

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Abstract

In addition to coding efficiency, the scalable extension of H.264/AVC provides good functionality for video adaptation in heterogeneous environments. Fine grain scalability (FGS) is a technique to extract video bitstream at the finest quality level under the given bandwidth. In this paper, an architecture of FGS encoder with low external memory bandwidth and low hardware cost is proposed. Up to 99% of bandwidth reduction can be attained by the proposed scan bucket algorithm, early context modeling with context reduction, and first scan pre-encoding. The area-efficient hardware architecture is implemented by layer-wise hardware reuse. Besides, three design strategies for enhancement layer coder are explored so that the trade-off between external memory bandwidth and silicon area is allowed. The proposed hardware architecture can real-time encode HDTV 1920脳1080 video with two FGS enhancement layers at 200 MHz working frequency, or HDTV 1280脳720 video with three FGS enhancement layers at 130 MHz working frequency.