Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
A Link Adaptation Scheme for Improving Throughput in the IEEE 802.11 Wireless LAN
LCN '02 Proceedings of the 27th Annual IEEE Conference on Local Computer Networks
Software-defined radio: basics and evolution to cognitive radio
EURASIP Journal on Wireless Communications and Networking
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Reconfigurable systems using FPGAs are of growing interest for the design and implementation of software defined radio transceivers. By reconfiguring an FPGA, its hardware resources can be reused and shared to provide multiple functionalities on a single device. This paper investigates power savings by means of partial reconfiguration for implementing two link adaptation algorithms. These algorithms provide variable performance in terms of spectral efficiency and hardware utilization at different average SNRs. In order to obtain the best tradeoff between (i) spectral efficiency and (ii) area and power consumption, we propose an efficient implementation that switches between the two algorithms by means of partial reconfiguration. Our experimental results show that our implementation provides a high spectral efficiency and, for certain SNR regions, reduces the hardware resources and thereby the power consumption.