Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision

Authors:
Tarek Ould Bachir;Jean-Pierre David
Affiliations:
-;-
Venue:
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Year:
2010

Citing 0
Cited 2

Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits

Mathematics and Computers in Simulation

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Abstract

In this paper, we discuss the feasibility of a floating-point accumulator (FPACC) on modern high-end FPGA devices. We explore different implementation scenarios and propose new FPACC architectures for both single and double precision floating-point addends. The proposed strategies can be easily adapted to the implement a multiply-accumulator (FPMAC), with one or two rounding stages, in both single and double precision as well. All the aforementioned designs are characterized by high operating frequencies (ranging from 130 to 300 MHz) and moderate occupation area (from 300 to 800 slices) when implemented on the VC5VSX50T FPGA, an entry level Virtex 5 from Xilinx.