A tool for power and phase noise optimization in frequency synthesizers

Authors:
Zhongtao Fu;Alyssa Apsel
Affiliations:
Cornell University, Ithaca, USA 14853;Cornell University, Ithaca, USA 14853
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2010

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Abstract

In this paper, we present a CAD technique to design low-power and low phase noise integrated frequency synthesizers. This technique introduces a key parameter, Phase Noise per Unit Power, which correlates phase noise and power among all the sub-circuits in the frequency synthesizer. By correlating the performance of all the independent circuits together, sophisticated synthesizer design and optimization can be significantly simplified. We demonstrate a 1.8 GHz frequency synthesizer design in a 0.18 μm CMOS process achieving 驴132 dBc/Hz phase noise at 100 kHz offset with less than 4.3 mW power consumption.