A timing-accurate modeling and simulation environment for networked embedded systems
Proceedings of the 40th annual Design Automation Conference
Network Emulation in the Vint/NS Simulator
ISCC '99 Proceedings of the The Fourth IEEE Symposium on Computers and Communications
NIST Net: a Linux-based network emulation tool
ACM SIGCOMM Computer Communication Review
MoteLab: a wireless sensor network testbed
IPSN '05 Proceedings of the 4th international symposium on Information processing in sensor networks
XORs in the air: practical wireless network coding
Proceedings of the 2006 conference on Applications, technologies, architectures, and protocols for computer communications
EmStar: a software environment for developing and deploying wireless sensor networks
ATEC '04 Proceedings of the annual conference on USENIX Annual Technical Conference
High-performance timing simulation of embedded software
Proceedings of the 45th annual Design Automation Conference
IEEE Transactions on Information Theory
IEEE Transactions on Information Theory
Flexible and efficient co-simulation of networked embedded devices
Proceedings of the 24th symposium on Integrated circuits and systems design
Efficient execution of networked MPSoC models by exploiting multiple platform levels
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
IEEE/ACM Transactions on Networking (TON)
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In this paper, we present the design and implementation of a general, flexible hardware-aware network platform which takes hardware processing behavior into consideration to accurately evaluate network performance. The platform adopts a network-hardware co-simulation approach in which the NS-2 network simulator supervises the network-wide traffic flow and the SystemC hardware simulator simulates the underlying hardware processing in network nodes. In addition, as a case study, we implemented wireless all-to-all broadcasting with network coding on the platform. We analyze the hardware processing behavior during the algorithm execution and evaluate the overall performance of the algorithm. Our experimental results demonstrate that hardware processing has a significant impact on the algorithm performance and hence should be taken into consideration in the algorithm design. We expect that this hardwareaware platform will become a very useful tool for more accurate network simulations and optimal designs of processingintensive applications.