High throughput and low power dissipation in QCA pipelines using Bennett clocking

Authors:
Marco Ottavi;Salvatore Pontarelli;Erik DeBenedictis;Adelio Salsano;Peter Kogge;Fabrizio Lombardi
Affiliations:
IEEE;IEEE;IEEE;IEEE;IEEE;IEEE
Venue:
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Year:
2010

Citing 5
Cited 0

Time/space trade-offs for reversible computation

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The Physical Limits of Computing

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Introduction to reversible computing: motivation, progress, and challenges

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Reversible computation with quantum-dot cellular automata (QCA)

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Logical reversibility of computation

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Abstract

This paper presents a detailed analysis of an architectural pipeline scheme for Quantum-dot Cellular Automata (QCA); this scheme utilizes the so-called Bennett clocking for attaining high throughput and low power dissipation. In this arrangement, computation stages (utilizing Bennett clocking) and memory stages combine the low power dissipation of reversible computing with the high throughput feature of a pipeline. An example of the application of the proposed scheme to an XOR tree circuit (parity generator) is presented; a detailed analysis of throughput and power consumption is provided to show the effectiveness of the proposed architectural solution for QCA.