A Parallel ASIC Architecture for Efficient Fractal Image Coding
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
Architecture for fractal image compression
Journal of Systems Architecture: the EUROMICRO Journal
IEEE Transactions on Visualization and Computer Graphics
ICPR '04 Proceedings of the Pattern Recognition, 17th International Conference on (ICPR'04) Volume 2 - Volume 02
Fractal image compression with variance and mean
ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 2
Schema genetic algorithm for fractal image compression
Engineering Applications of Artificial Intelligence
A fast classification based method for fractal image encoding
Image and Vision Computing
Fractal image compression using visual-based particle swarm optimization
Image and Vision Computing
Computers & Mathematics with Applications
DCT based simple classification scheme for fractal image compression
Image and Vision Computing
Secure semi-blind watermarking based on iteration mapping and image features
Pattern Recognition
Image compression with a hybrid wavelet-fractal coder
IEEE Transactions on Image Processing
Image coding based on a fractal theory of iterated contractive image transformations
IEEE Transactions on Image Processing
The effectiveness of image features based on fractal image coding for image annotation
Expert Systems with Applications: An International Journal
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Fractal coding algorithm has many applications including image compression. In this paper a classification scheme is presented which allows the hardware implementation of the fractal coder. High speed and low power consumption are the goal of the suggested design. The introduced method is based on binary classification of domain and range blocks. The proposed technique increases the processing speed and reduces the power consumption while the qualities of the reconstructed images are comparable with those of the available software techniques. In order to show the functionality of the proposed algorithm, the architecture was implemented on a FPGA chip. The application of the proposed hardware is shown in image compression. The resulted compression ratios, PSNR error, gate count, compression speed and power consumption are compared with the existing designs. Other applications of the proposed design are feasible in certain fields such as mass-volume database coding and also in video coder's block matching schemes.