Techniques and tools for implementing IEEE 754 floating-point arithmetic on VLIW integer processors

  • Authors:
  • Claude-Pierre Jeannerod;Christophe Mouilleron;Jean-Michel Muller;Guillaume Revy;Christian Bertin;Jingyan Jourdan-Lu;Hervé Knochel;Christophe Monat

  • Affiliations:
  • Université de Lyon, France;Université de Lyon, France;Université de Lyon, France;Université de Lyon, France;STMicroelectronics Compilation Expertise Center, Grenoble, France;STMicroelectronics Compilation Expertise Center, Grenoble, France;STMicroelectronics Compilation Expertise Center, Grenoble, France;STMicroelectronics Compilation Expertise Center, Grenoble, France

  • Venue:
  • Proceedings of the 4th International Workshop on Parallel and Symbolic Computation
  • Year:
  • 2010

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Abstract

Recently, some high-performance IEEE 754 single precision floating-point software has been designed, which aims at best exploiting some features (integer arithmetic, parallelism) of the STMicroelectronics ST200 Very Long Instruction Word (VLIW) processor. We review here the techniques and software tools used or developed for this design and its implementation, and how they allowed very high instruction-level parallelism (ILP) exposure. Those key points include a hierarchical description of function evaluation algorithms, the exploitation of the standard encoding of floating-point data, the automatic generation of fast and accurate polynomial evaluation schemes, and some compiler optimizations.