Matrix analysis
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Digital Image Processing (3rd Edition)
Digital Image Processing (3rd Edition)
Statistical timing analysis with two-sided constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A statistical framework for post-silicon tuning through body bias clustering
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Comparative analysis of conventional and statistical design techniques
Proceedings of the 44th annual Design Automation Conference
Post-silicon timing characterization by compressed sensing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Synthesizing a representative critical path for post-silicon delay prediction
Proceedings of the 2009 international symposium on Physical design
Proceedings of the 2009 International Conference on Computer-Aided Design
Analyzing the impact of process variations on parametric measurements: novel models and applications
Proceedings of the Conference on Design, Automation and Test in Europe
Sparse signal reconstruction from limited data using FOCUSS: are-weighted minimum norm algorithm
IEEE Transactions on Signal Processing
IEEE Transactions on Information Theory
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Timing Analysis: From Basic Principles to State of the Art
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Toward efficient spatial variation decomposition via sparse regression
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 49th Annual Design Automation Conference
Cross-layer virtual observers for embedded multiprocessor system-on-chip (MPSoC)
Proceedings of the 11th International Workshop on Adaptive and Reflective Middleware
Provably complete hardware trojan detection using test point insertion
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
The expensive cost of testing and characterizing parametric variations is one of the most critical issues for today's nanoscale manufacturing process. In this paper, we propose a new technique, referred to as Bayesian Virtual Probe (BVP), to efficiently measure, characterize and monitor spatial variations posed by manufacturing uncertainties. In particular, the proposed BVP method borrows the idea of Bayesian inference and information theory from statistics to determine an optimal set of sampling locations where test structures should be deployed and measured to monitor spatial variations with maximum accuracy. Our industrial examples with silicon measurement data demonstrate that the proposed BVP method offers superior accuracy (1.5x error reduction) over the VP approach that was recently developed in [12].