Using simple abstraction to reinvent computing for parallelism
Communications of the ACM
On best-effort utility accrual real-time scheduling on multiprocessors
OPODIS'10 Proceedings of the 14th international conference on Principles of distributed systems
Towards liquid service oriented architectures
Proceedings of the 20th international conference companion on World wide web
An efficient, dynamically adaptive method to tolerate transient faults in multi-core systems
EWDC '11 Proceedings of the 13th European Workshop on Dependable Computing
Multicore OSes: looking forward from 1991, er, 2011
HotOS'13 Proceedings of the 13th USENIX conference on Hot topics in operating systems
Forty data communications research questions
ACM SIGCOMM Computer Communication Review
Efficiently speeding up sequential computation through the n-way programming model
Proceedings of the 2011 ACM international conference on Object oriented programming systems languages and applications
Actor-eUML for concurrent programming
ER'11 Proceedings of the 30th international conference on Advances in conceptual modeling: recent developments and new directions
Identifying hotspots in a program for data parallel architecture: an early experience
Proceedings of the 5th India Software Engineering Conference
An efficient scheduler of RTOS for multi/many-core system
Computers and Electrical Engineering
Model-Driven Development with eUML-ARC
Proceedings of the 27th Annual ACM Symposium on Applied Computing
Thermal management of a many-core processor under fine-grained parallelism
Euro-Par'11 Proceedings of the 2011 international conference on Parallel Processing
Retrofitted parallelism considered grossly sub-optimal
HotPar'12 Proceedings of the 4th USENIX conference on Hot Topics in Parallelism
Efficient Parallel Implementations of Multiple Sequence Alignment using BSP/CGM Model
Proceedings of Programming Models and Applications on Multicores and Manycores
Improving execution unit occupancy on SMT-based processors through hardware-aware thread scheduling
Future Generation Computer Systems
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Designers now accept that although transistors will still get smaller and more numerous on each chip, they aren't going to operate faster than they do toady.And if you tried to incorporate all those transistors into one giant microprocessor, you might well end up with a device that couldn't compute any faster than the chip it was replacing, which explains the shift to assembling them into multiple microprocessor cores instead.