Low power logic for statistical inference

  • Authors:

  • Benjamin Vigoda;David Reynolds;Jeffrey Bernstein;Theophane Weber;Bill Bradley

  • Affiliations:

  • Lyric Semiconductor, Inc., Cambridge, MA, USA;Lyric Semiconductor, Inc., Cambridge, MA, USA;Lyric Semiconductor, Inc., Cambridge, MA, USA;Lyric Semiconductor, Inc., Cambridge, MA, USA;Lyric Semiconductor, Inc., Cambridge, MA, USA

  • Venue:
  • Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
  • Year:
  • 2010

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Abstract

Efficient hardware implementations of statistical inference continue to grow in importance for a wide range of computing applications. While CPU cycles are increasingly being used for statistical inference, transistors are also becoming increasingly statistical. For implementing statistical algorithms, could it be that statistical electronic substrates are a feature rather than a bug? We show that inference models can often be built from local constraints, and explain the gate-level mathematical functions required for the resulting inference solver. We suggest that signals should consist of probabilistic populations of particles representing samples from a probability distribution, with gate functions acting to transform these ensembles. Using this mapping from statistical physics to statistical inference, we present Bayesian logic circuits as highly efficient alternatives to digital standard cell libraries. Novel VLSI architectures based on Bayesian logic circuits promise to consume orders of magnitude less power and silicon area compared to conventional digital processors.