A Number System with Continuous Valued Digits and Modulo Arithmetic
IEEE Transactions on Computers
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Understanding belief propagation and its generalizations
Exploring artificial intelligence in the new millennium
The Teramac Custom Computer: Extending the Limits with Defect Tolerance
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Highly fault-tolerant parallel computation
FOCS '96 Proceedings of the 37th Annual Symposium on Foundations of Computer Science
The Journal of Machine Learning Research
Continuous-time analog circuits for statistical signal processing
Continuous-time analog circuits for statistical signal processing
Reconfigurable Architecture for Autonomous Self-Repair
IEEE Design & Test
Survey of Stochastic Computation on Factor Graphs
ISMVL '07 Proceedings of the 37th International Symposium on Multiple-Valued Logic
IBM Journal of Research and Development
Proceedings of the 47th Design Automation Conference
Nonparametric belief propagation
CVPR'03 Proceedings of the 2003 IEEE computer society conference on Computer vision and pattern recognition
Factor graphs and the sum-product algorithm
IEEE Transactions on Information Theory
Using linear programming to Decode Binary linear codes
IEEE Transactions on Information Theory
Constructing free-energy approximations and generalized belief propagation algorithms
IEEE Transactions on Information Theory
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Efficient hardware implementations of statistical inference continue to grow in importance for a wide range of computing applications. While CPU cycles are increasingly being used for statistical inference, transistors are also becoming increasingly statistical. For implementing statistical algorithms, could it be that statistical electronic substrates are a feature rather than a bug? We show that inference models can often be built from local constraints, and explain the gate-level mathematical functions required for the resulting inference solver. We suggest that signals should consist of probabilistic populations of particles representing samples from a probability distribution, with gate functions acting to transform these ensembles. Using this mapping from statistical physics to statistical inference, we present Bayesian logic circuits as highly efficient alternatives to digital standard cell libraries. Novel VLSI architectures based on Bayesian logic circuits promise to consume orders of magnitude less power and silicon area compared to conventional digital processors.