Hierarchical correctness proofs for distributed algorithms
PODC '87 Proceedings of the sixth annual ACM Symposium on Principles of distributed computing
Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Forward and backward simulations I.: untimed systems
Information and Computation
On the correctness of transactional memory
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
Mechanical Verification of Transactional Memories with Non-transactional Memory Accesses
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Completeness and Nondeterminism in Model Checking Transactional Memories
CONCUR '08 Proceedings of the 19th international conference on Concurrency Theory
Software Transactional Memory on Relaxed Memory Models
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Verifying Concurrent Data Structures by Simulation
Electronic Notes in Theoretical Computer Science (ENTCS)
Nonblocking algorithms and backward simulation
DISC'09 Proceedings of the 23rd international conference on Distributed computing
Formal verification of a lazy concurrent list-based set algorithm
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Transactional memory, linking theory and practice
ACM SIGACT News
Proving isolation properties for software transactional memory
ESOP'11/ETAPS'11 Proceedings of the 20th European conference on Programming languages and systems: part of the joint European conferences on theory and practice of software
On the liveness of transactional memory
PODC '12 Proceedings of the 2012 ACM symposium on Principles of distributed computing
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We describe ongoing work in which we aim to formally specify a correctness condition for transactional memory (TM) called Weakest Reasonable Condition (WRC), and to facilitate fully formal and machine-checked proofs that TM implementations satisfy the condition. To precisely define the WRC condition, we express it using an I/O automaton. We similarly present another condition, called PRAG, which is more restrictive, but more closely reflects intuition about common TM implementation techniques. We sketch a simulation proof that PRAG implements WRC, allowing ourselves and others to focus more pragmatically on proofs of such implementations. We are working on modeling these conditions in the PVS language so that we can construct and check such proofs precisely and mechanically. We are also working towards proving that some popular TM implementations satisfy the PRAG condition, starting with simple coarse-grained versions and refining them to model realistic implementations.