Compiler driven architecture design space exploration for DSP workloads: a study in software programmability versus hardware acceleration

Authors:
Michael C. Brogioli;Joseph R. Cavallaro
Affiliations:
School of Electrical and Computer Engineering, Rice University, Houston, Texas;School of Electrical and Computer Engineering, Rice University, Houston, Texas
Venue:
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Year:
2009

Citing 5
Cited 0

The SimpleScalar tool set, version 2.0

ACM SIGARCH Computer Architecture News
Unified assign and schedule: a new approach to scheduling for clustered register file microarchitectures

MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Microarchitectural exploration with Liberty

Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Spinach: a liberty-based simulator for programmable network interface architectures

Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Reconfigurable heterogeneous dsp/fpga based embedded architectures for numerically intensive computing workloads

Reconfigurable heterogeneous dsp/fpga based embedded architectures for numerically intensive computing workloads

Quantified Score

Hi-index	0.00

Visualization

Abstract

Wireless communications and video kernels contain vast instruction and data level parallelism that can far outstrip programmable high performance DSPs. Hardware acceleration of these bottlenecks is commonly done at the cost of software flexibility. Many vendors, however, view software as intellectual property and prefer a software solution that is a proprietary implementation. The paper uses a research compiler for architectural design space exploration to present comparisons between compiler generated scalable software programmable DSP architectures versus hardware acceleration implementations. It shows that scaled up compiler generated software programmable DSP architectures can be attractive alternatives to nonprogrammable hardware acceleration.