Low error rate LDPC decoders

Authors:
Zhengya Zhang;Lara Dolecek;Pamela Lee;Venkat Anantharam;Martin J. Wainwright;Brian Richards;Borivoje Nikolić
Affiliations:
Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor;Department of Electrical Engineering, University of California, Los Angeles;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley
Venue:
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Year:
2009

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Abstract

Low-density parity-check (LDPC) codes have been demonstrated to perform very close to the Shannon limit when decoded iteratively. However challenges persist in building practical high-throughput decoders due to the existence of error floors at low error rate levels. We apply high-throughput hardware emulation to capture errors and error-inducing noise realizations, which allow for in-depth analysis. This method enables the design of LDPC decoders that operate without error floors down to very low bit error rate (BER) levels. Such emulation-aided studies facilitate complex systems designs.