The MicroGrid: a scientific tool for modeling computational gridsr
Proceedings of the 2000 ACM/IEEE conference on Supercomputing
On Building Parallel & Grid Applications: Component Technology and Distributed Services
CLADE '04 Proceedings of the 2nd International Workshop on Challenges of Large Applications in Distributed Environments
A Metadata Catalog Service for Data Intensive Applications
Proceedings of the 2003 ACM/IEEE conference on Supercomputing
Benchmarking XML processors for applications in grid web services
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
Performance of multithreaded chip multiprocessors and implications for operating system design
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
An End-to-End Web Services-Based Infrastructure for Biomedical Applications
GRID '05 Proceedings of the 6th IEEE/ACM International Workshop on Grid Computing
The coming wave of multithreaded chip multiprocessors
International Journal of Parallel Programming
Performance Implications of Cache Affinity on Multicore Processors
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
The impact of multicore on math software
PARA'06 Proceedings of the 8th international conference on Applied parallel computing: state of the art in scientific computing
Performance impact of resource conflicts on chip multi-processor servers
PARA'06 Proceedings of the 8th international conference on Applied parallel computing: state of the art in scientific computing
| Hi-index | 0.00 |
There is a critical need to develop new programming paradigms for grid middleware tools and applications to harness the opportunities presented by emerging multi-core processors. Implementations of grid middleware and applications that do not adapt to the programming paradigm when executing on emerging processors can severely impact the overall performance. In this paper we focus on the utilization of the L2 cache, which is a critical shared resource on Chip Multiprocessors. The access pattern of the shared L2 cache, which is dependent on how the application schedules and assigns processing work to each thread, can either enhance or undermine the ability to hide memory latency on a multi-core processor. None of the current grid simulators and emulators provides feedback and fine-grained performance data that is essential for a detailed analysis. In this paper, using the feedback from an emulation framework, we present performance analysis and provide recommendations on how processing threads can be scheduled on multi-core nodes to enhance the performance of a class of grid applications that requires processing of large-scale XML data. In particular, we discuss the gains associated with the use of the adaptations we have made to the Cache-Affinity and Balanced-Set scheduling algorithms to improve L2 cache performance, and hence the overall application execution time.