Clock buffer polarity assignment with skew tuning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A reconfigurable clock polarity assignment flow for clock gated designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A novel clock tree synthesis (CTS) method is proposed that improves the reliability of an integrated circuit system through reducing the peak current on the power/ground rails drawn by the clock tree buffers. The proposed CTS method entails the integration of XOR gates at one level of the clock tree to enable polarity assignment for peak current reduction. Unlike previous polarity assignment methods, the skew of the generated clock tree with XORs is preserved as the physical layout of the clock tree is preserved during the polarity assignment process. Furthermore, the proposed clock tree permits the implementation of most of the previous polarity assignment methods through configurability of the control input of the XOR gates. Experimental results show that the peak current on the power/ground rails of the clock tree is reduced by an average of 55.2% without any degradation in the original clock skew.