An implementation of the Hamlyn sender-managed interface architecture
OSDI '96 Proceedings of the second USENIX symposium on Operating systems design and implementation
High performance RDMA-based MPI implementation over infiniBand
International Journal of Parallel Programming - Special issue I: The 17th annual international conference on supercomputing (ICS'03)
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
Trapeze/IP: TCP/IP at near-gigabit speeds
ATEC '99 Proceedings of the annual conference on USENIX Annual Technical Conference
Optimization of sparse matrix-vector multiplication on emerging multicore platforms
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
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Hybrid computing systems that combine specialized accelerators with general-purpose processors are now being used to improve performance in many application areas. However, processing of network communications by the accelerators is often a significant bottleneck to the performance of the hybrid system. At the same time, the powerful yet underutilized general-purpose processors of the hybrid system are well suited to processing significant levels of network traffic. In this paper, we propose a novel asymmetric network data flow control system optimized for data stream processing. The system allows the general-purpose processors in a hybrid system to take complete control of network data movement. The system uses remote direct memory access to allow direct communication between the general-purpose processors and the main memories of the accelerators, with no network processing overhead on the accelerators. The accelerators only perform read and write operations with respect to the main memory. Our Cell Broadband EngineA implementation of the system returns a high throughput of up to 934 MB/s, directly communicating with multiple processor cores with full data flow control to multiple processor cores, while eliminating the network processing bottleneck on the accelerator system. Furthermore, our implementation demonstrates excellent performance scalability when targeting increasing numbers of processor cores on the accelerator system.