Implementing extreme upsampling filters with a multiply-less architecture

  • Authors:

  • Andrew Laffely;Balasubramanian Ramakrishnan;Chayil Timmerman;Huan Yao;Jason Hillger

  • Affiliations:

  • Colorado Springs, CO;The MITRE Corporation, Bedford, MA;MIT Lincoln Laboratory, Lexington, MA;MIT Lincoln Laboratory, Lexington, MA;MIT Lincoln Laboratory, Lexington, MA

  • Venue:
  • MILCOM'09 Proceedings of the 28th IEEE conference on Military communications
  • Year:
  • 2009

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Abstract

For ease of implementation, communications systems have been steadily converted to digital implementations. FPGA technologies and high-quality, high-speed DACs have enabled this trend. While this is commonly done for modern high bit-rate communications systems, legacy systems like the MIL-STD-188-165A modem are not often considered. One issue is the need to up-sample these slower standards by factors of tens of thousands in order to interface them with the modulation system. This paper presents an architectural case study on the implementation of a direct digital synthesis MILSTD- 188-165A modem. It briefly describes a multiplyless single stage filter architecture with unlimited up-sampling capabilities. The filter implements a Farrow type design. By selecting the appropriate filter coefficients from a set of look-up-tables (LUT) the filter can be designed to suppress harmonic distortion below the required filter mask. Mathematical evaluation of these properties proves that a reasonable size LUT of 1024×14 bits is sufficient to suppress harmonics below - 60dB. A full analysis of harmonic suppression vs. LUT size is included to extend this work beyond the MIL-STD-188-165A case study.