VLSI implementation of image segmentation processor for brain MRI

Authors:
K. J. Shanthi;M. Sasikumar
Affiliations:
SCT College of Engineering, Trivandrum, India;Marian Engineering College, Trivandrum, India
Venue:
Proceedings of the 1st Amrita ACM-W Celebration on Women in Computing in India
Year:
2010

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Abstract

In this paper we present VLSI implementation of an automatic segmentation algorithm for Magnetic Resonance Images (MRI) of brain. The FPGA architecture incorporates all the functional units to realize the algorithm. The hardware implementation for threshold based segmentation is proposed. The processor capabilities can be extended to compute volume of the brain MRI. The experimental signal analysis and the resource requirement of the target device are also presented here.