RF and mixed signal circuits for a DVB-H receiver

  • Authors:
  • Sunil L. Khemchandani;Javier Pino;Enrique López-Morillo;Unai Alvarado;Dailos Ramos-Valido;Bernardo Palomo;Fernando Muñoz Chavero

  • Affiliations:
  • Institute for Applied Microlectronics (IUMA), University of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain 35017;Institute for Applied Microlectronics (IUMA), University of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain 35017;School of Engineering, Department of Electronic Engineering, University of Seville, Sevilla, Spain 41092;CEIT and Tecnun, University of Navarra, San Sebastián, Spain 20015;Institute for Applied Microlectronics (IUMA), University of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain 35017;School of Engineering, Department of Electronic Engineering, University of Seville, Sevilla, Spain 41092;School of Engineering, Department of Electronic Engineering, University of Seville, Sevilla, Spain 41092

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2010

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper presents a tutorial on RF and mixed signal circuits design for a digital video broadcasting-handheld tuner. A detailed description of the wideband low noise amplifier, the mixer, the synthesizer and the ADC, which are the most challenging components of a receiver, are carried out. Requirements relative to frequency range, sensitivity, noise figure, linearity, phase noise gain and dynamic range are discussed. The LNA uses a cascode configuration, combining a resistive loaded LNA with a conventional resistive shunt-feedback, in order to achieve a low power, low noise and wide bandwidth. The mixer uses a classical Gilbert cell configuration. The VCO employs techniques like emitter degeneration, capacitor divider, and optimum bias for minimum noise to improve phase noise requirements and oscillation amplitude. There are two ADC structures, one of which is a delta sigma ADC. The blocks are implemented in a AMS 0.35 μm BiCMOS process.