A power efficient baseband engine for multiuser mobile MIMO-OFDMA communications

Authors:
Jung-Mao Lin;Hsin-Yi Yu;Yu-Jen Wu;Hsi-Pin Ma
Affiliations:
Laboratory for Reliable Computing, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan;MStar Inc., Hsinchu, Taiwan and Laboratory for Reliable Computing, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan;Laboratory for Reliable Computing, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan;Laboratory for Reliable Computing, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2010

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Abstract

In this paper, the authors present a configurable and power efficient multiuser MIMO-OFDMA baseband processor for uplink mobile communications. To solve the carrier frequency offset (CFO) problem in multiuser transmission, an inter-carrier interference-based (ICI-cancellation-based) CFO estimator is implemented based on an iterative search criterion of minimum signal-to-interference-noise (SINR) ratio. Compared to the state-of-the-art methods, the proposed CFO estimator is more robust to transmission configurations (MIMO and multiuser) and CFO variations. Moreover, the authors propose an efficient architecture that saves 78% of the hardware complexity compared to the direct implemented architecture by employing Taylor series expansion for ICI/multiple-access interference (MAI) cancellation. Meanwhile, a 2-D linear channel estimator is also proposed to assist the CFO estimator and track the time-variant multipath channel. Two kinds of MIMO detector, vertical Bell Laboratory layered space-time (V-BLAST) and V-BLAST with maximum likelihood (V-ML), are adopted to minimize output latency and achieve the best ML bit-error-rate (BER) performance. An ASIC fabricated by 0.13 µm 1P8M CMOS technology is measured with 2.31 Mbps/mW power efficiency and less than 1.5 dB implementation loss. In addition, the whole transceiver is integrated and verified by a system-on-chip (SoC) platform to demonstrate its efficacy.