CMOS two-stage amplifier design approach

  • Authors:

  • Ahmed Reda Abd El-mon'm;Ahmed Wahba Abdallah

  • Affiliations:

  • Electronics and Communication Dept., Zagazig University, Zagazig, Egypt;Electronics and Communication Dept., Zagazig University, Zagazig, Egypt

  • Venue:
  • ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
  • Year:
  • 2010

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Abstract

This paper is a simple way to describe the design approach of a two-stage CMOS operational amplifier single power supply by using an algorithm manner. Based on a clear understanding of the required specifications, the proposed approach is developed to drive capacitive load (CL). This paper describes also measuring these specifications and improves it to get a good performance. The Dc gain, Gain band width product (GBWP), Slew Rate(SR), Input Common Mode Range (ICMR), Output Swing, Phase Margin, Gain Margin, Input offset voltage, Total Harmonic Distortion (THD), Power Supply Rejection Ratio (PSRR) and Power dissipation are considered in the proposed algorithm. This design is based on 0.13 µm IBM-CMOS process parameters.