FPGA implementation for real time encryption engine for real time video

  • Authors:
  • Jayashri E. Patil;A. D. Shaligram

  • Affiliations:
  • IsquareIT, ESD & VLSI department, Pune, India;Pune University, Electronics Science Deprtment, Pune, India

  • Venue:
  • ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
  • Year:
  • 2010

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Abstract

The paper titled FPGA Implementation of Real Time Encryption Engine for Real Time Video Encryption is an attempt to implement crypto cores for three different algorithms viz. AES, 3DES and Twofish so that to achieve real time encryption and decryption of video data from a real time source. The crypto core encryptor feeds the decryptor with an encrypted data with a private key cryptographic algorithm so that uninterrupted video streaming performance can be achieved with the system. The user key for cryptographic algorithms remains fixed for both encryptor and decryptor. The output is observed for a Digital Camera VGA picture input on a VGA monitor. The multiple implementations of the crypto cores add to the flexibility in terms of future modifications to the design. Each of the private key encryption algorithms was considered separately for an HDL implementation. The implementation was tested for synthesizable components. The system was then migrated to internal pattern encryption and decryption for the fixed available pattern and was tested for the same. The last stage consisted of applying the same to the external video signal available from the Camera unit interface. Each stage was complemented by the simulation of the behavioral model. Thus six different systems were developed which form the encryption decryption pairs for each possibility with the respective algorithm in hand.