Performance analysis of 65 nm nMOS using CoSi2and TiSi2

  • Authors:

  • Megat Mohd Izhar Sapeli;Taib Ziad Mohamad;Badariah Bais;M. Najib Harif

  • Affiliations:

  • -;Faculty of Engineering, Universiti Kebangsaan Malaysia, Bangi, Malaysia;Faculty of Engineering, Universiti Kebangsaan Malaysia, Bangi, Malaysia;Faculty of Applied Science, Universiti Teknologi MARA Negeri Sembilan, Kuala Pilah, Negeri Sembilan, Malaysia

  • Venue:
  • ISTASC'10 Proceedings of the 10th WSEAS international conference on Systems theory and scientific computation
  • Year:
  • 2010

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Abstract

In this project, two sets of 65 nm technology nMOS using TiSi2 and CoSi2 as the silicide layer were fabricated by using ATLAS module while the electrical properties for both devices were simulated using ATHENA module from SILVACO software. Three variables were varied in this project. By using Taguchi Method L9 array, 9 set of experiments were conducted for each silicide, and domination of those three variables toward the value of VTH were determined. The finding showed that the value of VTH using Co as the silicide layer had fulfilled with ITRS suggestion compared to Ti which was around 0.2 V. For ID-VD and ID-VG relationship, both silicides showed no obvious difference. In terms of structure, it was shown that silicide utilizing Co had a thicker layer at the side region compared to Ti which was thinner. In determining the domination of the three variables toward the VTH, it was shown that the gate dielectric thickness was the most dominant factor, followed by silicide annealing temperature and lastly the silicide diffusion time.